Semiconductor devices

ABSTRACT

A semiconductor device includes a substrate including a recess, the recess being positioned below an isolation region and having a side portion including a plurality of stepped portions, a plurality of gate electrodes spaced apart from each other on the substrate, and stacked in a direction perpendicular to an upper surface of the substrate, a channel structure passing between a first set of the plurality of gate electrodes, and the isolation region passing between a second set of the plurality of gate electrodes, the isolation region extending from the upper surface of the substrate and having an inclined lateral surface.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Continuation of U.S. application Ser. No.15/988,053, filed on May 24, 2018, which claims benefit of priority toKorean Patent Application No. 10-2017-0165077, filed on Dec. 4, 2017 inthe Korean Intellectual Property Office, the entire contents of whichare incorporated herein by reference in its entirety.

BACKGROUND 1. Field

Some example embodiments relate to semiconductor devices.

2. Description of Related Art

Electronic devices have gradually become smaller, while still processinglarge amounts of data. Accordingly, there is a desire to increase thedegree of integration of semiconductor memory devices used in suchelectronic products. In order to improve the degree of integration ofsemiconductor memory devices, flat memory devices, including memorycells having a flat transistor structure, have continued to be scaleddown. In recent years, vertical memory devices, in which memory cells,having a vertical transistor structure instead of a planar transistorstructure, are stacked, have been proposed.

SUMMARY

Some example embodiments provide a semiconductor device in which theoccurrence of bridge defects between gate electrodes and between thegate electrodes and a common source line may be reduced, and a slit (ora void) may be reduced or prevented from being formed within the commonsource line.

Some example embodiments provide a semiconductor device having improvedreliability.

Some example embodiments provide a method of fabricating a semiconductordevice, in which the occurrence of bridge defects between gateelectrodes and between the gate electrodes and a common source line maybe reduced and a slit (or a void) may be reduced or prevented from beingformed within the common source line.

Some example embodiments provide a method of fabricating a semiconductordevice having improved reliability.

According to some example embodiments, a semiconductor device includes asubstrate including a recess, the recess being positioned below anisolation region and having a side portion including a plurality ofstepped portions. The semiconductor device further includes a pluralityof gate electrodes spaced apart from each other on the substrate, andstacked in a direction perpendicular to an upper surface of thesubstrate. The semiconductor device further includes a channel structurepassing between a first set of the plurality of gate electrodes. Thesemiconductor device further includes the isolation region passingbetween a second set of the plurality of gate electrodes, the isolationregion extending from the upper surface of the substrate and having aninclined lateral surface.

According to some example embodiments, a semiconductor device includes asubstrate including a recess, the recess including a first region, asecond region and a third region having different widths. Thesemiconductor device further includes a stack structure including aplurality of gate electrodes and a plurality of mold insulating layersalternately stacked on the substrate. The semiconductor device furtherincludes a common source line passing through the stack structure tocontact at least the first region of the recess, the common source lineextending on the substrate in a direction.

According to some example embodiments, a semiconductor device includes asubstrate including a recess, the recess including a first region havinga first width, a second region having a second width greater than thefirst width, and a third region having a third width greater than thesecond width. The semiconductor device further includes a plurality ofstack structures each including a plurality of gate electrodes and aplurality of insulating layers alternately stacked on the substrate; aplurality of channel structures passing through the plurality of stackstructures to extend in a direction perpendicular to an upper surface ofthe substrate. The semiconductor device further includes a plurality ofspacers between the stack structures, the plurality of spacers on therecess of the substrate and extending on the substrate in a direction,the spacers contacting at least lateral surfaces of the third region.

BRIEF DESCRIPTION OF DRAWINGS

The above, and other aspects, features, and advantages of the presentdisclosure will be more clearly understood from the following detaileddescription when taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a plan view illustrating a portion of a cell region of asemiconductor device, according to some example embodiments;

FIG. 2 is a cross-sectional view of a semiconductor device including acommon source line having upper and lower regions, according to someexample embodiments;

FIG. 3 is a cross-sectional view of a semiconductor device including acommon source line having a single region, according to some exampleembodiments;

FIG. 4 is a cross-sectional view of a semiconductor device including arecess having four regions of different widths, according to someexample embodiments;

FIGS. 5A through 5I are cross-sectional views of a method of fabricatinga semiconductor device, according to some example embodiments;

FIG. 6 is a cross-sectional view of a semiconductor device not includingthe semiconductor pattern of FIG. 2, according to some exampleembodiments;

FIG. 7 is a cross-sectional view of a semiconductor device including amemory cell array region and a peripheral circuit region, according tosome example embodiments;

FIG. 8 is a cross-sectional view of a semiconductor device in which thethickness of the insulating spacer varies such that the thicknessproximate to the substrate is greater than the thickness remote from thesubstrate, according to some example embodiments; and

FIG. 9 is a cross-sectional view of a semiconductor device in which thethickness of the insulating spacer varies such that the thicknessproximate to the substrate is less than the thickness remote from thesubstrate, according to some example embodiments.

DETAILED DESCRIPTION

Hereinafter, some example embodiments will be described with referenceto the attached drawings.

FIG. 1 is a plan view illustrating a portion of a cell region of asemiconductor device, according to some example embodiments; and FIG. 2is a cross-sectional view taken along line I-I′ of the semiconductordevice FIG. 1 including a common source line having upper and lowerregions.

Referring to FIGS. 1 and 2, the semiconductor device, according to someexample embodiments, may include a substrate 3, a stack structure ST, achannel structure 42, a common source line 78, and an insulating spacer72. The stack structure ST may include mold insulating layers 8 andconductive layers 57. The channel structure 42 may include a dielectricstructure 30, a semiconductor layer 33, a filling insulating layer 36, aconductive pad 39, and a semiconductor pattern 38. The semiconductordevice may further include a contact plug 84 connected to the conductivepad 39, and a bit line 87 connected to the contact plug 84.

The substrate 3 may include a semiconductor material, such as a group IVsemiconductor material, a group III-V compound semiconductor material,or a group II-VI compound semiconductor material. For example, thesubstrate 3 may be a monocrystalline silicon substrate or asilicon-on-insulator (SOI) substrate.

The stack structure ST may be disposed on the substrate 3. The stackstructure ST may include the mold insulating layers 8 and the conductivelayers 57. The conductive layers 57 may be disposed between the moldinsulating layers 8. The mold insulating layers 8 and the conductivelayers 57 may be alternately and repeatedly stacked on the substrate 3.The conductive layers 57 may be spaced apart from each other on thesubstrate 3, and may be stacked in a second direction perpendicular toan upper surface of the substrate 3. The mold insulating layers 8 may bespaced apart from each other on the substrate 3, and may be stacked inthe second direction perpendicular to the upper surface the substrate 3.Each of the conductive layers 57 may include a first conductive layer 55and a second conductive layer 56.

In an example, the conductive layers 57 may include select gateelectrodes 57 s and 57 g and cell gate electrodes 57 w. The conductivelayers 57 may be gate electrodes.

A lowermost select gate electrode 57 g of the select gate electrodes 57s and 57 g may be a ground select line (GSL), and an uppermost selectgate electrode 57 s thereof may be a string select line (SSL).

The cell gate electrodes 57 w may be disposed between the uppermostselect gate electrode 57 s and the lowermost select gate electrode 57 g.The cell gate electrodes 57 w may be word lines of memory cells. Thecell gate electrodes 57 w may be spaced apart from each other in thesecond direction perpendicular to the upper surface of the substrate 3.

The mold insulating layers 8 may include a first lower mold insulatinglayer 5L disposed between the lowermost select gate electrode 57 g andthe substrate 3, a second lower mold insulating layer 5U disposedbetween the lowermost select gate electrode 57 g and a lowermost cellgate electrode of the cell gate electrodes 57 w, intermediate moldinsulating layers 6 disposed between the cell gate electrodes 57 w andbetween an uppermost cell gate electrode of the cell gate electrodes 57w and the uppermost select gate electrode 57 s, and an upper moldinsulating layer 7 disposed on the uppermost select gate electrode 57 s.The first lower mold insulating layer 5L, contacting an upper surface ofthe substrate 3, may be thinner than each of the intermediate moldinsulating layers 6. The second lower mold insulating layer 5U and theupper mold insulating layer 7 may be thicker than each intermediate moldinsulating layer 6.

The channel structure 42 may be disposed within a channel hole CHpassing through the stack structure ST. For example, the channelstructure 42 may pass through the stack structure ST. The channel holeCH may have a width narrowing toward a lower region thereof.

The channel structure 42 may include the semiconductor layer 33extending in the second direction perpendicular to the upper surface ofthe substrate 3, and the dielectric structure 30 disposed between thesemiconductor layer 33 and the stack structure ST. The semiconductorlayer 33 may be a channel layer.

The dielectric structure 30 may include a first dielectric layer 21, asecond dielectric layer 24, and a third dielectric layer 27 sequentiallyformed within the channel hole CH. The second dielectric layer 24 may beinterposed between the first and third dielectric layers 21 and 27. Thesecond dielectric layer 24 may contact the first and third dielectriclayers 21 and 27. The third dielectric layer 27 may contact thesemiconductor layer 33. The first dielectric layer 21 may be a blockinglayer. The first dielectric layer 21 may include, for example, a siliconoxide. The second dielectric layer 24 may be a charge storage layer. Thesecond dielectric layer 24 may be a charge trapping layer. The seconddielectric layer 24 may include a silicon nitride, a silicon oxynitride,and a silicon-rich silicon oxide. The third dielectric layer 27 may be atunneling layer. The third dielectric layer 27 may be formed of asilicon oxide or a silicon oxide-based dielectric.

The channel structure 42 may further include the filling insulatinglayer 36 filling a space within the semiconductor layer 33, and theconductive pad 39 disposed on the filling insulating layer 36. Thefilling insulating layer 36 may contact the semiconductor layer 33. Thefilling insulating layer 36 may be formed of an insulating material, forexample, a silicon oxide. The conductive pad 39 may be formed of aconductive material, for example, polycrystalline silicon having n-typeconductivity.

The semiconductor pattern 38 may be disposed within the channel hole CH.The semiconductor pattern 38 may be disposed below the semiconductorlayer 33. The semiconductor pattern 38 may be an epitaxial layer grownfrom the substrate 3, using a selective epitaxial growth (SEG) process.The semiconductor pattern 38 may contact the semiconductor layer 33. Aninsulating layer 63 may be disposed between the semiconductor pattern 38and the lowermost select gate electrode 57 g. The insulating layer 63may contact the semiconductor pattern 38. The insulating layer 63 may beformed of a silicon oxide.

Fourth dielectric layers 54 may be interposed between the conductivelayers 57 and the mold insulating layers 8, and may extend between theconductive layers 57 and the dielectric structure 30. The fourthdielectric layer 54 and the first dielectric layer 21 may constitute ablocking layer.

The fourth dielectric layer 54 may be formed of a high-k dielectricmaterial. The high-k dielectric material may be at least one of analuminum oxide (Al2O3), a tantalum oxide (Ta2O3), a titanium oxide(TiO2), a yttrium oxide (Y2O3), a zirconium oxide (ZrO2), a zirconiumsilicon oxide (ZrSixOy), a hafnium oxide (HfO2), a hafnium silicon oxide(HfSixOy), a lanthanum oxide (La2O3), a lanthanum aluminum oxide(LaAlxOy), a lanthanum hafnium oxide (LaHfxOy), a hafnium aluminum oxide(HfAlxOy), and a praseodymium oxide (Pr2O3). The fourth dielectric layer54 may be formed of a crystallized aluminum oxide.

A first upper insulating layer 45 may be disposed on the stack structureST and the channel structure 42. The first upper insulating layer 45 maybe formed of an insulating material, such as a silicon oxide.

The common source line 78 may be disposed within an isolation region OPpassing through the first upper insulating layer 45 and the stackstructure ST and extending into the substrate 3. The isolation region OPmay extend in a first direction parallel to the upper surface of thesubstrate 3. Lateral surfaces of the isolation region OP may be flat,and may not have an uneven pattern, and the width of the isolationregion OP may narrow as the isolation region OP approaches the substrate3. Lateral surfaces of the conductive layers 57 may be coplanar withthose of the mold insulating layers 8. The common source line 78 maypass through the first upper insulating layer 45 and the stack structureST. The common source line 78 may extend in the first direction parallelto the upper surface of the substrate 3, and may cut the first upperinsulating layer 45 and the stack structure ST in the second directionperpendicular to the upper surface of the substrate 3.

A recess RCS may be formed in the upper surface of the substrate 3 belowthe isolation region OP. The common source line 78 may be disposed inthe recess RCS. The recess RCS may have side portions including aplurality of stepped portions SP. The width of an upper portion of therecess RCS may be similar to or the same as that of a lower portion ofthe isolation region OP. Lateral surfaces of the upper portion of therecess RCS may be coplanar with those of the isolation region OP. Thewidth of the upper portion of the recess RCS may be greater than that ofthe lower portion of the recess RCS. The recess RCS may include a firstregion R1, a second region R2, and a third region R3 having differentwidths. The second region R2 may be disposed on the first region R1, andthe third region R3 may be disposed on the second region R2. The firstwidth W1 of the first region R1 may be narrower than the second width W2of the second region R2, and the second width W2 of the second region R2may be narrower than the third width W3 of the third region R3. Thethird width W3 of the third region R3 may be similar to or the same asthe width of the lower portion of the isolation region OP. Each oflateral surfaces of the third region R3 may be coplanar with a lateralsurface of a lowermost mold insulating layer, for example, the firstlower mold insulating layer 5L, contacting the upper surface of thesubstrate 3, of the mold insulating layers 8.

The common source line 78 may be connected to a lowermost portion of therecess RCS. The common source line 78 may contact the lowermost portionof the recess RCS, for example, the first region R1 of the recess RCS.The common source line 78 may include the lowermost portion of therecess RCS, for example, a lower region contacting the first region R1and an upper region disposed on the lower region, and the width of theupper region may be greater than that of the lower region. The width ofthe upper region may narrow as the upper region approaches the substrate3.

In an example, the common source line 78 may be formed of a conductivematerial. The conductive material may include at least one of a metal,such as Ti, Ta, Cu, Al, or W, and a metal nitride, such as TiN, TaN, orTiAlN.

The insulating spacer 72 may be disposed between the stack structure STand the common source line 78. The insulating spacer 72 may be disposedbetween the common source line 78 and the conductive layers 57, and maycontact the conductive layers 57 disposed on the isolation region OP.The insulating spacer 72 may extend in the first direction parallel tothe upper surface of the substrate 3, for example, in a similardirection or the same direction as that in which the common source line78 may extend. The insulating spacer 72 may include a silicon oxide, asilicon nitride, a silicon oxynitride, or combinations thereof.

A lower portion of the insulating spacer 72 may contact at least aportion of the stepped portions SP of the recess RCS. The lower portionof the insulating spacer 72 may contact the second region R2 and thethird region R3 of the recess RCS. As described above, the common sourceline 78 may contact the first region R1 of the recess RCS.

The insulating spacer 72 may have a first thickness T1 at a portion on alateral surface of a lowermost gate electrode, for example, a lateralsurface of the lowermost select gate electrode 57 g, and may have asecond thickness T2 at a portion on a lateral surface of an uppermostgate electrode, for example, a lateral surface of the uppermost selectgate electrode 57 s, and the second thickness T2 may be similar to orthe same as the first thickness T1. A first distance between thelowermost select gate electrode 57 g and the common source line 78 maybe similar to or the same as a second distance between the uppermostselect gate electrode 57 s and the common source line 78.

An impurity region 75 may be disposed within the substrate 3 below thecommon source line 78. The impurity region 75 may be disposed below therecess RCS of the substrate 3. The impurity region 75 may extend in thefirst direction parallel to the upper surface of the substrate 3, forexample, a similar direction or the same direction as that in which thecommon source line 78 may extend. The impurity region 75 may havedifferent conductivity type from the substrate 3 adjacent to theimpurity region 75. For example, the impurity region 75 may have n-typeconductivity, and the substrate 3 adjacent to the impurity region 75 mayhave p-type conductivity. The impurity region 75 may include n-typeimpurities, and the substrate 3 may include p-type impurities.

The impurity region 75 and the conductive pad 39 may have the sameconductivity type. For example, the impurity region 75 and theconductive pad 39 may have n-type conductivity. The conductive pad 39may be a drain region, and the impurity region 75 may be a sourceregion.

The channel structure 42, passing through the stack structure ST, may beprovided as a plurality of channel structures 42. For example, thechannel structures 42 may be arranged along the common source line 78 inzigzag form as depicted in FIG. 1.

A second upper insulating layer 81 may be disposed on the first upperinsulating layer 45 and the common source line 78. The contact plug 84may pass through the first and second upper insulating layers 45 and 81,and may electrically connect to the conductive pad 39 of the channelstructure 42. The bit line 87 may be disposed on the second upperinsulating layer 81 to be electrically connected to the contact plug 84.

FIG. 3 is a cross-sectional view of a semiconductor device including acommon source line having a single region, according to some exampleembodiments. FIG. 3 illustrates only a cross section corresponding to anenlarged region of the recess RCS of FIG. 2.

Referring to FIG. 3, a common source line 78 a may be disposed in therecess RCS formed in the upper surface of the substrate 3. The recessRCS may include a first region R1, a second region R2, and a thirdregion R3 having different widths. A first width W1 of the first regionR1 may be narrower than a second width W2 of the second region R2, andthe second width W2 of the second region R2 may be narrower than a thirdwidth W3 of the third region R3.

The common source line 78 a may contact the lowermost portion of therecess RCS, for example, the first region R1 of the recess RCS. Unlikethe common source line 78 of FIG. 2, the common source line 78 a mayinclude a single region. The width of the common source line 78 a maynarrow as the common source line 78 a approaches the substrate 3.

The thickness of an insulating spacer 72 a may be greater than that ofthe insulating spacer 72 of FIG. 2. The thickness of the insulatingspacer 72 a disposed on the first lower mold insulating layer 5L may bethe same as the sum of widths of two stepped portions SP in contact withthe insulating spacer 72 a. A lower portion of the insulating spacer 72a may contact the second region R2 and the third region R3 of the recessRCS.

FIG. 4 is a cross-sectional view of a semiconductor device including arecess having four regions of different widths, according to someexample embodiments. FIG. 4 illustrates only a cross sectioncorresponding to the enlarged region of the recess RCS of FIG. 2.

Referring to FIG. 4, a common source line 78 b may be disposed in arecess RCS′ formed in the upper surface of the substrate 3. The recessRCS′ may include a first region R1, a second region R2, a third regionR3, and a fourth region R4 having different widths. A first width W1 ofthe first region R1 may be narrower than a second width W2 of the secondregion R2, the second width W2 of the second region R2 may be narrowerthan a third width W3 of the third region R3, and the third width W3 ofthe third region R3 may be narrower than a fourth width W4 of the fourthregion R4. The widths of stepped portions SP may be narrower than thoseof the stepped portions SP of FIG. 2 or 3.

The common source line 78 b may contact a lowermost portion of therecess RCS′ and a portion of the stepped portions SP. Unlike the commonsource line 78 of FIG. 2, the common source line 78 b may include aplurality of regions having different widths, such that the shape of thecommon source line 78 b may correspond to that of the recess RCS′. Forexample, the common source line 78 a may include three regions havingdifferent widths, such that the shape of the common source line 78 a maycorrespond to that of the recess RCS′.

The thickness of an insulating spacer 72 b may be less than that of theinsulating spacer 72 of FIG. 2. The thickness of the insulating spacer72 b disposed on the first lower mold insulating layer 5L may be similarto or the same as the width of a single stepped portion SP in contactwith the insulating spacer 72 b. A lower portion of the insulatingspacer 72 b may contact the fourth region R4 of the recess RCS′.

FIGS. 5A through 5I are cross-sectional views of a method of fabricatinga semiconductor device, according to some example embodiments. Themethod of fabricating a semiconductor device, illustrated in FIG. 1 or2, will be described hereinafter with reference to FIGS. 5A through 5I.FIGS. 5A through 5I are the cross-sectional views taken along line I-I′of FIG. 1.

Referring to FIG. 5A, a substrate 3 may be provided. The substrate 3 maybe a semiconductor substrate. A plurality of mold insulating layers 8and a plurality of sacrificial layers 13 may be formed to be alternatelyand repeatedly stacked on the substrate 3. The mold insulating layers 8and the sacrificial layers 13 may constitute a mold structure. The moldinsulating layers 8 may be formed of a material having etch selectivitywith respect to a material of the sacrificial layers 13. For example,the mold insulating layers 8 may be formed of a silicon oxide, and thesacrificial layers 13 may be formed of a silicon nitride.

The mold insulating layers 8 may include a first lower mold insulatinglayer 5L, a second lower mold insulating layer 5U disposed on the firstlower mold insulating layer 5L, a plurality of intermediate moldinsulating layers 6 disposed on the second lower mold insulating layer5U, and an upper mold insulating layer 7 disposed on the intermediatemold insulating layers 6.

The first lower mold insulating layer 5L may be thinner than each of theintermediate mold insulating layers 6. The second lower mold insulatinglayer 5U may be thicker than each intermediate mold insulating layer 6.The upper mold insulating layer 7 may be thicker than each intermediatemold insulating layer 6. The sacrificial layers 13 may have a similarthickness or substantially the same thickness.

A channel hole CH may be formed through the mold structure, for example,the mold insulating layers 8 and the sacrificial layers 13. The channelhole CH may be provided as a plurality of channel holes CHs, and mayexpose the substrate 3. While the channel hole CH is formed, a recessmay be formed in an upper portion of the substrate 3. The channel holeCH may include an upper portion having a width greater than that of alower portion.

A semiconductor pattern 38 may be formed within the recess below thechannel hole CH by a SEG process using the substrate 3 as a seed layer.The semiconductor pattern 38 may be a silicon epitaxial layer. An uppersurface of the semiconductor pattern 38 may be higher than a lowersurface of the second lower mold insulating layer 5U, and may be lowerthan an upper surface of the second lower mold insulating layer 5U.

Referring to FIG. 5B, a first dielectric layer 21, a second dielectriclayer 24, and a third dielectric layer 27 may be sequentially formed onthe substrate 3 having the channel hole CH and the semiconductor pattern38. A sacrificial spacer 29 may be formed on the third dielectric layer27 within the channel hole CH, and then the semiconductor pattern 38 maybe exposed by anisotropically etching the first to third dielectriclayers 21, 24, and 27, using the sacrificial spacer 29 as an etchingmask.

Referring to FIG. 5C, the sacrificial spacer 29 may be removed, and asemiconductor layer 33 may be formed. The semiconductor layer 33 mayconnect to the semiconductor pattern 38. When the sacrificial spacer 29is removed, an upper portion of the semiconductor pattern 38 may bepartially etched, so as to form a recess region. In this case, therecess region may be filled with the semiconductor layer 33. In someexample embodiments, the semiconductor layer 33 may be formed withoutremoving the sacrificial spacer 29.

A filling insulating layer 36 may be formed on the semiconductor layer33 to fill a portion of the channel hole CH, and a conductive pad 39 maybe formed to fill the remainder of the channel hole CH and cover thesemiconductor layer 33 and the filling insulating layer 36.

The first to third dielectric layers 21, 24 and 27 may constitute adielectric structure 30. The semiconductor pattern 38, the conductivepad 39, the semiconductor layer 33, the filling insulating layer 36, andthe dielectric structure 30 may constitute a channel structure 42.

Referring to FIG. 5D, a first upper insulating layer 45 may be formed tocover the channel structure 42 and the upper mold insulating layer 7. Apreparatory isolation region 51 may be formed through the first upperinsulating layer 45, the mold insulating layers 8, and the sacrificiallayers 13 in the second direction perpendicular to the upper surface ofthe substrate 3. A first preparatory recess RC1 may be formed in thesubstrate 3, while the preparatory isolation region 51 is formed.Subsequently, lateral opening portions 52 may be formed by selectivelyremoving the sacrificial layers 13 exposed by the preparatory isolationregion 51. For example, when the sacrificial layers 13 are siliconnitride layers and the mold insulating layers 8 are silicon oxidelayers, an isotropic etching process may be performed using an etchantcontaining phosphoric acid. The lateral opening portions 52 may extendfrom the preparatory isolation region 51 to spaces between the moldinsulating layers 8 in a horizontal direction, so as to expose portionsof a lateral surface of the channel structure 42 and a portion of alateral surface of the semiconductor pattern 38. By an oxidationprocess, an insulating layer 63 may be formed on the lateral surface ofthe semiconductor pattern 38 exposed by the lateral opening portions 52.

Referring to FIG. 5E, a fourth dielectric layer 54 and a conductivematerial layer 57 a may be formed to fill the lateral opening portions52.

The fourth dielectric layer 54 may be formed by forming an amorphousmetal oxide film and then performing a heat treatment process forcrystallization thereon. Selectively, after the heat treatment process,a surface of the metal oxide film may be etched. The heat treatmentprocess may be a spike-rapid thermal processing (RTP) process conductedin an inert gas atmosphere.

Forming the conductive material layer 57 a may include forming a firstconductive material layer 55 a covering the fourth dielectric layer 54,and a second conductive material layer 56 a covering the firstconductive material layer 55 a and filling the lateral opening portions52, within the lateral opening portions 52.

The fourth dielectric layer 54 and the conductive material layer 57 amay also be formed on a lateral surface of the preparatory isolationregion 51 and on the first upper insulating layer 45. The fourthdielectric layer 54 and the conductive material layer 57 a may also beformed on a surface of the first preparatory recess RC1.

Referring to FIG. 5F, conductive layers 57 may be formed to be separatedfrom each other in the second direction perpendicular to the uppersurface of the substrate 3.

By a wet etching process, portions of the conductive material layer 57 aformed on the lateral surface of the preparatory isolation region 51, onthe first upper insulating layer 45, and on the surface of the firstpreparatory recess RC1, may be removed.

In this operation, the mold insulating layers 8 may be protruded furtherthan the conductive layers 57. Each of the conductive layers 57 mayinclude a first conductive layer 55 and a second conductive layer 56.

Referring to FIG. 5G, an isolation region OP may be formed by removingprotruding portions of the mold insulating layers 8.

By a dry etching process, the protruding portions of the mold insulatinglayers 8 may be removed. The dry etching process may be performed usingan etching gas including a C4F6 gas, a C4F8 gas, or combinationsthereof. Lateral surfaces of the conductive layers 57 may be coplanarwith those of the mold insulating layers 8 within the isolation regionOP. Thus, because a slit or void may not be formed within a commonsource line 78 to be described later in a process of forming the commonsource line 78, the melting of insulating spacer 72 by a fluorine F2 gasremaining within the slit or void may be reduced or prevented. Further,portions of the first conductive layer 55 that may remain along theprotruding portions of the mold insulating layers 8 may removedtogether, and thus a defect in a bridge between the conductive layers 57may be reduced or prevented.

In this operation, a second preparatory recess RC2 may be formed in anupper surface of the substrate 3. The second preparatory recess RC2 maybe deeper than the first preparatory recess RC1. The second preparatoryrecess RC2 may have a side portion including a single stepped portionSP. The stepped portion SP may be formed by removing the protrudingportions of the mold insulating layers 8 and then etching a portion ofthe substrate 3 below the protruding portions. The second preparatoryrecess RC2 may include an upper region and a lower region havingdifferent widths. The width of the upper region of the secondpreparatory recess RC2 may be greater than that of the first preparatoryrecess RC1. The width of the lower region of the second preparatoryrecess RC2 may be substantially similar to or the same as that of thefirst preparatory recess RC1.

Referring to FIG. 5H, insulating spacers 72 may be formed on lateralsurfaces of the isolation region OP.

The insulating spacers 72 may be formed by forming an insulatingmaterial layer covering the lateral surfaces of the isolation region OPand an upper surface of the second preparatory recess RC2 and performingan etchback process.

In this operation, a recess RCS may be formed in the substrate 3. Therecess RCS may have a side portion having two stepped portions SP. Theinsulating spacer 72 may be formed on the stepped portions SP of therecess RCS. A lower portion of the insulating spacer 72 may include abent portion formed along the shape of the recess RCS. A portion of thesubstrate 3 may be exposed by the isolation region OP.

An impurity region 75 may be formed below the recess RCS. Impurities maybe injected by an ion implantation process, subsequent or prior toforming the insulating spacer 72. The impurity region 75 may include,for example, n-type impurities.

Referring to FIG. 5I, a common source line 78 may be formed to fillbetween a space between the insulating spacers 72.

The common source line 78 may be formed by depositing a conductivematerial filling the isolation region OP (FIG. 5H) and performing aplanarization process. The common source line 78 may be formed of aconductive material. The conductive material may be formed of at leastone of, for example, a metal nitride, a metal silicide, and a metal.

Referring again to FIG. 1 or 2, a second upper insulating layer 81 maybe formed on the first upper insulating layer 45 and the common sourceline 78. A contact plug 84 may be formed to pass through the first andsecond upper insulating layers 45 and 81 and to be electricallyconnected to the conductive pad 39 of the channel structure 42. Thecontact plug 84 may be formed of a metal silicide, a metal nitride,and/or a metal. A bit line 87 may be formed on the second upperinsulating layer 81 to be electrically connected to the contact plug 84.The bit line 87 may be formed of a conductive material, for example, ametal nitride, such as TiN or TaN, and a metal, such as W, Al, or Cu.

Unlike the above-mentioned fabrication method, in a fabrication methodaccording to some example embodiments, conductive layers 57 may beformed by a dry etching process, such that the conductive layers 57 maybe separated from each other in the second direction perpendicular tothe upper surface of the substrate 3.

By the dry etching process, portions of the conductive material layers57 a formed on the lateral surfaces of the preparatory isolation region51, on the first upper insulating layer 45, and on the surface of thefirst preparatory recess RC1, may be removed first. Portions of the moldinsulating layers 8, exposed by the removal of the portions of theconductive material layer 57 a having covered the lateral surfaces ofthe preparatory isolation region 51, may be removed together with theportions of the conductive material layers 57 a by the dry etchingprocess. By the dry etching process, the mold insulating layers 8 andthe conductive material layers 57 a may be etched at a similar etchingrate or the same etching rate.

As described above, lateral opening portions and a second preparatoryrecess similar to or the same as those of FIG. 5G may be formed by thedry etching process able to etch the mold insulating layers 8 and theconductive material layers 57 a together. The dry etching process may beperformed using an etching gas including a Cl2 gas.

FIG. 6 is a cross-sectional view of a semiconductor device not includingthe semiconductor pattern of FIG. 2, according to some exampleembodiments.

Unlike the semiconductor device illustrated in FIG. 2, the semiconductordevice, illustrated in FIG. 6, may include the channel structure 42′ nothaving the semiconductor pattern 38. Thus, the semiconductor layer 33may directly contact the substrate 3.

The semiconductor device, illustrated in FIG. 6, may be fabricated bythe processes subsequent to those of FIG. 5B without performing the SEGprocess for forming the semiconductor pattern 38, described above withreference to FIG. 5A.

In the semiconductor device, according to the foregoing, the stackstructure ST, the channel structure 42′, the common source line 78, theinsulating spacer 72, the impurity region 75, and the bit line 87disposed on the substrate 3 may constitute a memory cell array region. Aperipheral circuit region, electrically connecting to such a memory cellarray region, may be formed on the substrate 3, and may be disposedexternally of the memory cell array region. The peripheral circuitregion may include a plurality of transistors. The arrangement of theperipheral circuit region is not limited thereto, and may be modified.

FIG. 7 is a cross-sectional view of a semiconductor device including amemory cell array region and a peripheral circuit region, according tosome example embodiments.

Referring to FIG. 7, the stack structure ST, the channel structure 42,the common source line 78, the insulating spacer 72, the impurity region75, and the bit line 87 disposed on a substrate 3′ may constitute amemory cell array region Cell. A peripheral circuit region Peri may bedisposed below the memory cell array region Cell. The memory cell arrayregion Cell may have the same structure as that illustrated in FIG. 2,but the substrate 3′ may include, for example, an amorphous orpolycrystalline semiconductor material.

The peripheral circuit region Peri may be formed on a base substrate103. The base substrate 103 may be a semiconductor substrate. Theperipheral circuit region Peri may include a plurality of transistors TRand a plurality of wirings ML. The peripheral circuit region Peri may becovered by a lower insulating layer 110 between the base substrate 103and the substrate 3′.

FIG. 8 is a cross-sectional view of a semiconductor device in which thethickness of the insulating spacer varies such that the thicknessproximate to the substrate is greater than the thickness remote from thesubstrate, according to some example embodiments.

Referring to FIG. 8, unlike the semiconductor device illustrated in FIG.2, the insulating spacer 72′ may have a first thickness T1′ at a portionon a lateral surface of a lowermost gate electrode, for example, alateral surface of the lowermost select gate electrode 57 g, and mayhave a second thickness T2′ at a portion on a lateral surface of anuppermost gate electrode, for example, a lateral surface of theuppermost select gate electrode 57 s, and the first thickness T1′ may begreater than the second thickness T2′. A first distance between thelowermost select gate electrode 57 g and the common source line 78 maybe greater than a second distance between the uppermost select gateelectrode 57 s and the common source line 78.

FIG. 9 is a cross-sectional view of a semiconductor device in which thethickness of the insulating spacer varies such that the thicknessproximate to the substrate is less than the thickness remote from thesubstrate, according to some example embodiments.

Referring to FIG. 9, unlike the semiconductor device illustrated in FIG.2, the insulating spacer 72″ may have a first thickness T1″ at a portionon a lateral surface of a lowermost gate electrode, for example, alateral surface of the lowermost select gate electrode 57 g, and mayhave a second thickness T2″ at a portion on a lateral surface of anuppermost gate electrode, for example, a lateral surface of theuppermost select gate electrode 57 s, and the first thickness T1″ may beless than the second thickness T2″. A first distance between thelowermost select gate electrode 57 g and the common source line 78 maybe less than a second distance between the uppermost select gateelectrode 57 s and the common source line 78.

As set forth above, according to some example embodiments, there may beprovided a semiconductor device in which the occurrence of bridgedefects between gate electrodes and between the gate electrodes and acommon source line may be reduced, and a slit (or a void) may be reducedor prevented from being formed within the common source line. Further, asemiconductor device having improved reliability may be provided.

While some example embodiments have been shown and described above, itwill be apparent to those skilled in the art that modifications andvariations could be made without departing from the scope of theappended claims.

1. (canceled)
 2. A semiconductor device comprising: a substrateincluding a recess, the substrate defining the recess to include a firstregion, a second region and a third region having different widths; astack structure including a plurality of gate electrodes and a pluralityof mold insulating layers alternately stacked on the substrate; a commonsource line passing through the stack structure to contact the substrateat the first region of the recess; and an insulating spacer between thestack structure and the common source line, the insulating spacerincluding silicon nitride.
 3. The semiconductor device of claim 2,wherein the common source line extends in a direction parallel to anupper surface of the substrate, and the insulating spacer includes acombination of a silicon compound containing oxygen and a siliconcompound containing nitrogen.
 4. The semiconductor device of claim 2,wherein the substrate defines a side portion of the recess to include aplurality of stepped portions.
 5. The semiconductor device of claim 2,wherein a first space between a lateral surface of a lowermost gateelectrode of the plurality of gate electrodes and the common source lineis different from a second space between a lateral surface of thesubstrate at the second region of the recess and the common source line,and a lower portion of the insulating spacer includes a bent portionformed according to a shape of the recess, and contacts the substrate atthe second region and the third region of the recess.
 6. Thesemiconductor device of claim 2, further comprising: a peripheralcircuit region below the substrate and on a base substrate, theperipheral circuit region including a plurality of transistors and aplurality of wirings, and the peripheral circuit region overlapping thestack structure in a direction perpendicular to an upper surface of thesubstrate.
 7. The semiconductor device of claim 2, wherein the secondregion is above the first region, the third region is above the secondregion, and a first width of the first region is narrower than a secondwidth of the second region, and the second width of the second region isnarrower than a third width of the third region, and a lateral surfaceof the third region is coplanar with a lateral surface of a lowermostmold insulating layer of the plurality of mold insulating layers, thelowermost mold insulating layer contacting an upper surface of thesubstrate.
 8. The semiconductor device of claim 4, wherein the recessfurther includes a fourth region above the third region, the fourthregion including one of the plurality of stepped portions, and thefourth region having a fourth width greater than a third width of thethird region, and the insulating spacer contacting the substrate at thefourth region of the recess.
 9. A semiconductor device comprising: asubstrate including a recess, the substrate defining the recess toinclude a first region, a second region and a third region havingdifferent widths; a stack structure including a plurality of gateelectrodes and a plurality of mold insulating layers alternately stackedon the substrate; a common source line passing through the stackstructure to contact the substrate at the first region of the recess;and an insulating spacer between the stack structure and the commonsource line, the insulating spacer including a silicon compoundcontaining nitrogen.
 10. The semiconductor device of claim 9, whereinthe common source line extends in a direction parallel to an uppersurface of the substrate, and the insulating spacer includes acombination of a silicon compound containing oxygen and the siliconcompound containing nitrogen.
 11. The semiconductor device of claim 9,wherein the substrate defines a side portion of the recess to include aplurality of stepped portions.
 12. The semiconductor device of claim 9,wherein a first space between a lateral surface of a lowermost gateelectrode of the plurality of gate electrodes and the common source lineis different from a second space between a lateral surface of thesubstrate at the second region of the recess and the common source line,and a lower portion of the insulating spacer includes a bent portionformed according to a shape of the recess, and contacts the substrate atthe second region and the third region of the recess.
 13. Thesemiconductor device of claim 9, further comprising: a peripheralcircuit region below the substrate and on a base substrate, theperipheral circuit region including a plurality of transistors and aplurality of wirings, and the peripheral circuit region overlapping thestack structure in a direction perpendicular to an upper surface of thesubstrate.
 14. The semiconductor device of claim 9, wherein the secondregion is above the first region, the third region is above the secondregion, and a first width of the first region is narrower than a secondwidth of the second region, and the second width of the second region isnarrower than a third width of the third region, and a lateral surfaceof the third region is coplanar with a lateral surface of a lowermostmold insulating layer of the plurality of mold insulating layers, thelowermost mold insulating layer contacting an upper surface of thesubstrate.
 15. The semiconductor device of claim 9, further comprising:an impurity region below the recess and having n-type impurities. 16.The semiconductor device of claim 9, further comprising: a first upperinsulating layer on the stack structure, and wherein the common sourceline cuts the first upper insulating layer and the stack structure in adirection parallel to an upper surface of the substrate, and verticallypenetrates the first upper insulating layer.
 17. A semiconductor devicecomprising: a substrate including a recess, the substrate defining therecess to include a first region, a second region and a third regionhaving different widths; a stack structure including a plurality of gateelectrodes and a plurality of mold insulating layers alternately stackedon the substrate; a peripheral circuit region below the substrate and ona base substrate, the peripheral circuit region including a plurality oftransistors and a plurality of wirings, the peripheral circuit regionoverlapping the stack structure in a direction perpendicular to an uppersurface of the substrate; a common source line passing through the stackstructure to contact the substrate at the first region of the recess,the common source line extending in a direction parallel to an uppersurface of the substrate; and an insulating spacer between the stackstructure and the common source line, the insulating spacer including asilicon compound containing nitrogen.
 18. The semiconductor device ofclaim 17, wherein the insulating spacer includes a combination a siliconcompound containing oxygen and the silicon compound containing nitrogen.19. The semiconductor device of claim 17, wherein the substrate definesa side portion of the recess to include a plurality of stepped portions.20. The semiconductor device of claim 17, wherein a first space betweena lateral surface of a lowermost gate electrode of the plurality of gateelectrodes and the common source line is different from a second spacebetween a lateral surface of the substrate at the second region of therecess and the common source line, and a lower portion of the insulatingspacer includes a bent portion formed according to a shape of therecess, and contacts the substrate at the second region and the thirdregion of the recess.
 21. The semiconductor device of claim 17, whereinthe second region is above the first region, the third region is abovethe second region, and a first width of the first region is narrowerthan a second width of the second region, and the second width of thesecond region is narrower than a third width of the third region, and alateral surface of the third region is coplanar with a lateral surfaceof a lowermost mold insulating layer of the plurality of mold insulatinglayers, the lowermost mold insulating layer contacting an upper surfaceof the substrate.